The present invention relates generally to the manufacture of semiconductor integrated circuits and more particularly to a method and a system for real-time in-situ interactive supervision of the semiconductor wafer fabrication process. In a dedicated tool controlled by a computer, a method is developed which includes the steps of monitoring in real-time in-situ a plurality of process parameters in parallel by an end-point controller. Analysis rules are developed to perform a comparison and associated rejection criteria are coded in the form of algorithms and likewise stored in a database. If a process deviation is detected, an alert code is flagged to signal an alarm and the adequate action is immediately taken and these data stored in the database may be used to up-date the operating conditions of a step before it takes place.
Due to the constant integration density increase, the fabrication processes that are used to date in the manufacture of semiconductor wafers for the production of integrated circuits (ICs) have to be very accurately controlled. For this reason, processing tools which are required to that end, are becoming more and more complex. A processing tool can include a plurality of chambers, and in turn, each chamber can run a great number of processing steps. For money saving and high throughputs, the wafer is generally processed in sequence via said plurality of chambers of the tool under computer control. The selection of the chamber depends on a number of factors such as: availability, contamination level, specialization, . . . etc.
New methods for tool and process characterization such as in-situ contamination monitoring, measurements, gas analysis and the like, are now of common use in the semiconductor industry. All these characterization techniques produce huge quantity of data of various types. In particular such data include the physical process parameters such as: gas flows, pressures, RF powers, temperatures, and the like, that are permanently under computer control during a determined step. Other data include results provided by controllers (e.g. etch rates) which continuously monitor the process and by measurement units.
FIG. 1 schematically shows a conventional system of the prior art referenced 10 that implements a typical process flow for processing semiconductor wafers. The description which follows will be made by reference to a multi-chamber RIE tool such as the AME 5000 manufactured by Applied Materials, Santa Clara, Calif., USA, that is adapted to perform a sequence of steps for etching different materials at the surface of the wafer. However, other tools such as deposition equipments and the like may be envisioned as well. Now turning to FIG. 1, system 10 is thus comprised of such a RIE etching tool 11 with a tool computer 12 associated thereto. As apparent from FIG. 1, tool 11 is only comprised of two chambers 11-1 and 11-2 for sake of simplicity, but in reality, it must be understood that it may have more, for instance, up to six independent chambers. Still for sake of simplicity, we will assume that each chamber performs the same sequence of processing steps, labelled A, B, . . . , I, . . . , X. A data bus referenced 13 provides the electrical connection between the tool chambers and the computer 12 for data flow exchange therebetween.
At initialization, computer 12 down-loads the physical process parameters of step A into chamber 11-1 or 11-2 as appropriate. Typical physical process parameters are gas flows, pressures, RF powers, temperatures and the like. Then, step A is performed and is generally stopped after a fixed time. This procedure applies for the other steps B, C, . . . X, whenever necessary. During these steps, computer 12 checks the different physical process parameters via data bus 12 for process control and only stops the current process if one of them passes beyond a predefined limit. A stop generally occurs after a serious hardware failure such as a RF power shut-down or a gas flow missing.
FIG. 2 describes an improved version of the system depicted in FIG. 1 now referenced 10xe2x80x2, the same elements bearing the same references. For sake of illustration, only three (A to C) and one (A) processing steps are performed in chambers 11-1 and 11-2 respectively. In addition to the tool 11, the computer 12 and the data bus 13 connected therebetween, the improved system 10xe2x80x2 includes additional equipments associated to each tool chamber. As apparent in FIG. 2, two etch end-point detection (EPD) controllers 14-1 and 14-2 are provided with optical fibers 15-1 and 15-2 to view the plasma inside chambers 11-1 and 11-2 respectively. The role of these EPD controllers is only to perform optical/interferometric measurements. An adequate EPD controller that can be used in system 10xe2x80x2 is the DIGISEM or DIGITWIN sold by SOFIE Instr., Arpajon, FRANCE. However, in the present application, xe2x80x9cEPDxe2x80x9d denotes either xe2x80x9cetch end point detectionxe2x80x9d or more generally xe2x80x9cend point detectionxe2x80x9d, for instance, if a deposition process is used instead of an etch process. Likewise, two control devices 16-1 and 16-2, typically particle counters, gas detectors, mass spectrometers and the like are associated to chambers 11-1 and 11-2 respectively. The nature of these control devices depends on the function: etching, deposition, . . . of the tool in consideration. Control devices are used by the operators for visual inspection of the on-going process, so that they may stop it in case of need, for instance, if a contamination in excess is detected by a particle counter. Finally, two measurement units 17-1 and 17-2 are necessary for intermediate and post-processing measurements to determine whether or not the wafer is still within the specifications at the output of each chamber. Note that, in some cases, measurement units 17-1 and 17-2 can designate a single and same unit 17. As apparent in FIG. 2, these measurement are respectively performed at the output of chambers 11-1 and 11-2. Measurement units and control devices are generally provided with a local database to record the main events for subsequent review by the operators at the end of the process. Data bus 18 provides the necessary electrical connection between the computer 12 and the EPD controllers 14-1 and 14-2 for an elementary data exchange. As a matter of fact, the role of EPD controllers is only to signal that the etch end point has been detected or if not, that the processing step hag reached the maximum allowed time for that determined step.
The operation of system 10xe2x80x2 is relatively simple. Let us assume that for sake of simplicity, that (1) only three steps labelled A to C are performed in the first chamber 11-1 with only two steps (A and C) monitored by EPD controller 14-1 and (2) only one step (A) is performed in chamber 11-2. First, computer 12 down-loads physical process parameters to chamber 11-1 via data bus 13 the way described above, and in the meantime, the identification number of the algorithm to be used in step A is sent to EPD controller 14-1 via bus 18. Starting step A in chamber 11-1 also starts the EPD controller 14-1 scanning of the selected etch end point parameter, typically a specific radiation wavelength that is emitted by a determined layer at the surface of the wafer. A surge in the signal representing this emission indicates that the end point has been reached. However, other parameters can be used as well. The signal transmitted via optic fiber 15-1 is processed in EPD controller 14-1 to detect the etch end point. In that case, a signal is emitted by EPD controller 14-1 via data bus 18 to inform computer 12 that the etch end point has been reached and that step A must be stopped. In the contrary, EPD controller 14-1 informs computer 12 that the maximum allowed time has been reached. Next, step B is initiated. The duration of this step is not monitored by EPD controller 14-1, so that it is therefore determined by a time fixed by the user. Let us assume that step C is performed the same way as step A, i.e. it is also monitored by EPD controller 14-1. Once step C has been completed, the wafer is sent to the measurement unit 17-1 to check whether or not its complies with the specifications. Only good wafers are loaded in chamber 11-2 to continue processing. Once step A is achieved in chamber 11-2, a new measurement step is performed in measurement unit 17-2. It is important to notice, that none of these steps A to C performed in the first chamber interferes with another, nor with the step performed in the second chamber. In other words, all these steps are sequentially performed without any influence of a previous step on the following step. As mentioned above, during these steps, computer 12 checks all different physical process parameters and stops current process only one of them passes beyond a predefined limit. Optionally, a summary of these physical process parameters can be uploaded in the database of computer 12 for subsequent analysis. However, the real status of the wafer after each processing step is totally unknown for the computer.
A better understanding of the complex interactions between the system 101 of FIG. 2 and the wafer fabrication process itself will be best understood by the following description made by reference to FIGS. 3 to 5 when the system 10xe2x80x2 is used to perform the so-called xe2x80x9cAB ETCHxe2x80x9d/xe2x80x9cAB STRIPxe2x80x9d in the course of the trench formation process in DRAM chips. The xe2x80x9cAB ETCHxe2x80x9d is comprised of three etching steps (labelled A, B and C) performed in sequence in the same chamber, i.e. 11-1 of the etch tool 11. The xe2x80x9cAB ETCHxe2x80x9d is followed by the xe2x80x9cAB STRIPxe2x80x9d, a single step (labelled A) in chamber 11-2 that aims to remove the photoresist material remaining after these three etching steps. The xe2x80x9cAB ETCH/AB STRIPxe2x80x9d process has been chosen because it is consistent with the above description made by reference to FIG. 2 but also because it is a good introduction to the method and system of the present invention. Please refer to European Pat. appl. No 756,318 for more details. The xe2x80x9cAB ETCHxe2x80x9d process will be first briefly summarized hereinbelow.
Let us consider FIG. 3 which is comprised of FIGS. 3A to 3D. Now turning to FIG. 3A, there is shown a portion of a semiconductor wafer illustrating a structure referenced 19 at the initial stage prior to the xe2x80x9cAB ETCHxe2x80x9d process properly said. Structure 19 to be etched includes a silicon substrate in which shallow trenches 20A and 20B have been selectively formed using an in-situ Si3N4 mask layer 21. These trenches are filled with TEOS SiO2 material by the deposition of a conformal layer 22. At this stage of the fabrication process, small and wide depressions referenced 23A and 23B are formed in layer 22 above trenches 20A and 20B respectively as shown in FIG. 3A. Planarization of structure 19 then requires the successive deposition of two photoresist layers. A photoresist layer (AB1) 24 with a thickness of 830 nm is first deposited onto the structure 22, then exposed, baked and developed as standard to leave a patterned layer referred to as AB1 mask still referenced 24. In essence, the aim of this mask 24 is to fill the wide depressions 23B and a determined amount of small depressions such as 23A. Next, a second 830 nm thick layer (AB2) 25 of the same photoresist is applied over layer 24, then baked. After this second step, we can consider that the wafer surface is coarsely planar.
Now, the coarsely planarized surface of the FIG. 3A structure will be transferred to the TEOS SiO2 layer 22 to produce a thinner but substantially planar layer of TEOS SiO2 all over the silicon wafer according to the xe2x80x9cAB ETCHxe2x80x9d process. The xe2x80x9cAB ETCHxe2x80x9d process is completed in three different steps labelled A to C. All these steps are achieved in a single chamber of the AME 5000 plasma etcher as mentioned above.
According to the first step, referred to as step A, the top resist layer 25 is etched until the surface of the TEOS SiO2 layer 22 (at mount locations) is reached. By means of an adequate algorithm, EPD controller 14-1 is used to detect the AB2 layer 25/TEOS SiO2 layer 22 interface, by detecting a SiO ray having a wavelength of 230.0 nanometers.
FIG. 4 shows the plot displayed on EPD controller 14-1 screen at the end of step A. Curves 26 and 27 respectively show signal S1 which illustrates the 230.0 nm SiO intensity as a function of time during this first step A and its derivative signal Sxe2x80x21. On the other hand, curves 28 and 29 respectively show signal S2 which illustrates the intensity of a CO ray having a wavelength of 483 nm and its derivative signal Sxe2x80x22. Signal Sxe2x80x22 allows to determine the etch rate of AB2 layer 25 as standard. Signals S1 and S2 result from optical measurements. Signals depicted in FIG. 4 are illustrative of a structure 19 without any defect and an etch process perfectly conducted. The surge that can be noticed in signal Sxe2x80x21 (curve 27) is used as the etch end point criteria for step A. A short over-etching is then conducted to terminate this step. At this stage of the process, the structure 19 is shown in FIG. 3B.
Now, the second step B is performed to remove a given amount (about 160 nm) of the AB1 photoresist and TEOS SiO2 layers with a different non selective etching chemistry. The resulting structure is shown in FIG. 3C.
In the third and last step C, the TEOS SiO2 layer 22 is etched using the AB1 resist layer as an in-situ mask. To that end, controller 14-1 now performs an interferometric measurement of the type described in European Pat. No 735,565 to Auda et al jointly assigned to IBM Corp. and SOFIE Inst. to determine the etch end-point. Briefly said, a light beam generated by a mercury lamp is applied to the wafer. According to that reference, two different wave-lengths are used to control the amount of TEOS SiO2 layer 22 etched from a given starting point so called xe2x80x9cRATE TIMExe2x80x9d.
FIG. 5 shows the plot displayed on EPD controller 14-1 screen at the end of step C. Curves 30 and 31 respectively illustrate signals S3 and S4 that are representative of the 404.7 nm and 435.8 nm Hg radiation intensity as a function of time. Curves 32 and 33 illustrate their respective derivative signals Sxe2x80x23 and Sxe2x80x24. Both wavelengths can be used for etch end point determination. The typical shape of curves 30 to 33 are still illustrative of a structure 19 without any defect and of an etch process correctly performed. The sine-shaped curves 30 and 31 allow an easy determination of the etch rates at step C. The reader may wish to consider the Auda et al reference for more details related to this particular measurement technique. At the end of the xe2x80x9cAB ETCHxe2x80x9d process, the targeted TEOS SiO2 thickness remains over the Si3N4 mask layer 21. The resulting structure is shown in FIG. 3D.
The interactions between the different constituting parts of system 10xe2x80x2 and the xe2x80x9cAB ETCH/AB STRIPxe2x80x9d process therefore read as follows. First, the wafer to be etched is introduced in chamber 11-1 of the AME 5000 plasma etcher tool 11. Then, the etch process of step A starts, so does EPD controller 14-1. When etch end point is found, step A is stopped. Then, step B is initiated. Once step B is finished after a fixed period of time, step C is completed as described by reference to step A. Finally, after completion of the whole sequence of steps A to C, the wafer is sent (may be true for some sample wafers only) to measurement unit 17-1 in order to determine whether the remaining TEOS layer 22 thickness is within specifications or not. If remaining TEOS layer 22 is too thin, the wafer is rejected. If remaining TEOS layer 22 is too thick, the wafer is sent back to the chamber 11-1 for rework. Reworked wafers are measured again. Good wafers are loaded in a cassette and then sent to chamber 11-2 for stripping the remaining of photoresist AB1 layer 24 according to step A of the xe2x80x9cAB STRIPxe2x80x9d process. After the xe2x80x9cAB STRIPxe2x80x9d process has been completed, the wafer is sent to measurement unit 17-2 to check if this step has been satisfactorily performed.
The above step sequence for a correctly processed wafer may be schematically summarized as follows.
1) Unload wafer from cassette and load wafer in chamber 11-1.
2) Run the three steps A to C of the xe2x80x9cAB ETCHxe2x80x9d process.
3) Measure the remaining TEOS SiO2 layer thickness in measurement unit 17-1. Dismiss bad wafer for rejection or rework.
4) Load wafer in chamber 11-2.
5) Run the single step A of the xe2x80x9cAB STRIPxe2x80x9d process.
6) Unload wafer from tool and load wafer in cassette.
6) Perform post-processing check in measurement unit 17-2. Dismiss bad wafer for rejection or rework.
7) Go to the next process.
The intermediate steps of loading/unloading the wafer into/from the cassette have not been mentioned for sake of simplicity.
The process flow showing the different processing/measurements steps conducted in their respective tools/equipments is shown in FIG. 6. As apparent from FIG. 6, because the TEOS SiO2 layer thickness needs to be checked in measurement unit 17-1 before it is sent to chamber 11-2, the xe2x80x9cAB ETCHxe2x80x9d process cannot be clusterized, i.e. a direct transfer between chambers 11-1 and 11-2 is impossible. In others words, this process cannot be qualified as xe2x80x9cin-situxe2x80x9d because the wafer leaves the vacuum of tool 11 for that measurement step. Finally, this sequence of steps terminates by another mandatory measurement step in measuring unit 17-2.
In addition, using EPD controller 14-1 to control steps A and C does no guarantee a correct xe2x80x9cAB ETCHxe2x80x9d process. Some serious problems that often occur at this stage of the fabrication process may lead to reject a number of wafers. One can distinguish among these problems, according to a coarse classification, those related to misprocessing errors, process drifts and tool failures. A typical mis-processing error consists to have AB1 or AB2 layer (or both) missing. For instance, if the AB2 layer 25 is missing, the EPD controller 14-1 will wait the occurrence of a transition in the Sxe2x80x21 signal (related to the 230 nm SiO ray) which will never happen. As a consequence, step A will stop at the end of the maximum allowed time. In this case, the wafer must be rejected because during this step, there has been performed an undesired over-etching of the AB1 mask layer 24 and of the TEOS SiO2 layer 22. The wafer is definitely damaged and is no longer reworkable. The other most commonly observed misprocessing errors are: a non-exposure of the AB1 photoresist layer 24, the TEOS SiO2 layer 22 thickness out of specifications or the TEOS SiO2 layer simply missing. A deposition of polymers on the view-port surface of the AME 5000 plasma etcher will produce process drifts that could be detrimental to keep the wafer within specifications. Finally, an electrical misfunction on the buses or a RF shut-down are typical examples of tool failures.
For these reasons, the xe2x80x9cAB ETCHxe2x80x9d process needs to be constantly under human control as it is the only way to react if a problem occurs. The operator must periodically adjust parameters in the course of the process depending on its evolution, making thereby very difficult any automation attempt. Moreover, because there is no possibility to intervene during the process, a problem is only detected when a wafer is extracted from a chamber, so that it is too late to save the wafer which is often no longer reworkable. As a matter of fact, with the FIG. 2 system, about 5% of the wafers are rejected at the end of the xe2x80x9cAB ETCHxe2x80x9d process. Finally, it has also to be noticed that the xe2x80x9cAB ETCHxe2x80x9d process is slow because the measurement step performed in unit 17-1 necessitates a wafer loading/unloading operation in the cassette before a transfer between the two chambers takes place.
In summary, none of the system configurations shown in FIGS. 1 and 2 is able to react in real-time in-line to any of the above mentioned problems during the current processing step: wafer misprocessing, process drifts, and tool failures to immediately undertake the right corrective action. Moreover, none of these systems is able to take profit of the wafer history (i.e. all the events that occurred to the wafer prior to the current step) to change a process parameter during the current step or in a subsequent step. Moreover, these system configurations result in non automated tools because no clusterization is possible, so that the totality of the wafer processing cannot be performed in-situ in a multi-chamber tool. Mandatory intermediate and post-processing measurement steps slacken the process flow. Consequently, it would be highly desirable to develop a method and a system that would get rid of all these drawbacks.
It is therefore a primary object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision.
It is another object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision that get rid of misprocessing errors, process drifts and tool failures by real-time detection thereof during wafer processing.
It is another object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision that significantly reduce the wafer rejection rate for increased manufacturing yields by stopping the processing or by-passing the next steps while the wafer is still reworkable.
It is another object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision that significantly reduce the wafer reworking.
It is another object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision that drastically reduce processing costs and turn-around time.
It is another object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision that obviate the necessity of having a permanent human control for better automation.
It is still another further object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision that eliminate all standard off-line measurements, including post-processing measurements to speed-up wafer processing and increase the daily going rate (DGR).
It is still another further object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision that allow to process only good wafers to avoid unnecessary processing time and wafer waste.
It is still another further object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision that allow a full clusterized (i.e. in-situ) process tracking all direct transfers, i.e. a direct transfer of the wafer from one chamber to another of the same tool without breaking the vacuum.
It is still another further object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision that incorporate in-situ measurements, the results of which are stored in a database to build the step/wafer history.
It is still another further object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision wherein the the key process parameters of a step are stored in a database at the end of the step to build the step/wafer history.
It is still another further object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision that take into account the previous step/wafer history during current wafer processing.
It is still another further object of the present invention to provide a method and a system for semiconductor wafer fabrication process real-time in-situ interactive supervision wherein data stored in the database are retrieved therefrom to up-date a process parameter before the step is started.
The accomplishment of these and other related objects is achieved by the supervisor and the supervision method of the present invention.
A preliminary but essential step of the method consists to establish an adequate database. First of all, for each step of the process, process engineers select a predetermined one or several process parameters that allow the system to monitor that step. The database first contains data relative to the evolution of selected process parameters during a certain step of the wafer fabrication process when this step takes place normally and the evolutions of these selected process parameters in case of identified deviations. These identified deviations are based on all the possible causes of wafer rejection based on experimental or empirical or other information known to the process engineers (hereinafter referred to as expert information). The process engineers define the set of analysis rules that permit to characterize these deviations and establish the corresponding rejection criteria. These rules are coded in the form of algorithms that are also stored in the database. These algorithms are thus adapted to subsequently monitor said selected process parameters during this step and detect any identified deviations. An alert code and an action, still based upon the expert information, are assigned to each deviation and coded the same way in the database. For instance, the current step can be stopped at any time in case of emergency or the next steps by-passed if so required by the alert code. The whole set of alert codes constitutes the alarms of this step in consideration. These operations are performed for each processing step of the wafer fabrication process and for each tool of the manufacturing line wherever possible.
Now, during a particular step of the wafer processing, the different monitoring equipments (EPD controllers, control devices, . . . ) that are selected to continuously monitor the selected process parameters for that step, generates data (e.g. electric signals) that are in real-time in-situ compared with the data stored in the database by said analysis algorithms. This analysis is performed in a dedicated unit referred to as a supervisor which receives data from said monitoring equipments and has an adequate connection with the database. If a deviation is detected, the supervisor emits the alert code to the computer controlling the process tool to flag an alarm and it takes an immediate and appropriate action; otherwise, the process is continued to its normal end.
At the end of that step, the key process parameters, the evolution of the selected process parameters during this step and the alert code (if any) are stored in the database. According to an important feature of the method and system of the present invention, the monitoring equipment is provided with a local measurement unit to perform in-situ measurements (e.g. a thickness) before the step takes place. The data related to these measurements are coded and also stored in the database. These data can be used either immediately or in a subsequent step to up-date some process parameters (e.g. an etch rate) of the step in consideration to modify the step current operating conditions. All the important data that are representative of the processing for that step constitutes xe2x80x9cstep reportxe2x80x9d of that step and is stored in the database. In the database, the wafer history is the sum of all the step reports for a particular process and a particular wafer. The wafer history is thus the essential element for this up-date. The sum of the xe2x80x9cwafer historyxe2x80x9d of all the wafers of a batch constitutes the xe2x80x9cbatch historyxe2x80x9d. In turn, the xe2x80x9cbatch historyxe2x80x9d of a plurality of batches can be exploited, in particular for statistics purposes, for instance for preventive/predictive maintenance. Among other advantages, one may note that only xe2x80x9cgoodxe2x80x9d wafers will be completely processed for higher throughputs and that a total clusterized in-situ wafer fabrication process is now possible.
The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as these and other objects and advantages thereof, will be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings.